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Strings in Verilog
A quick reference on a couple of ways to manipulate strings in Verilog HDL.
Declaration
There is no string data type is Verilog, so use the following to declare a register to hold a string.
reg[n*8:0] string;
Where the maximum length of the string is n characters. It takes 8 bits to store each character.
Usage
string = "Hello World"; $sdisplay("%s", string); // will get "Hello World"
Also, normal concatination will work, for the most part. So something like:
string = {"/path/to/file","/","filename",".txt"};
will result in a string useful to pass to $open to open a file.
For anything more advanced, a very good function is
$sformat(string,"%s %d %s",str1,num,str2);
would produce the string with the three varibles concatinated together and spaces in between.
//------------------------------------------------------------------------------------------------------------------------------------------
module vstring ();
function [10 *8 -1:0] int2str;
input [31:0] inum;
begin
int2str = 0;
while(inum > 0) begin
int2str = {"0" + (inum - (inum/10)*10), int2str[79:8]};
inum = inum / 10;
end
end
endfunction
function [256 *8 -1:0] strfilter;
input [256 *8 -1:0] iline;
input [7:0] cnum;
integer i;
begin
strfilter = 0;
for(i=0;(i<256)&&(cnum>0); i=i+1) begin
if(iline[2047:2040] != 0) begin
strfilter = {strfilter, iline[2047:2040]};
cnum = cnum -1;
end
iline = iline<<8;
end
while(cnum>0) begin
strfilter = {strfilter, 8'h0};
cnum = cnum -1;
end
end
endfunction
`define ULINE "./cpu/u"
reg [32 *8 -1:0] num32;
reg [ 2 *8 -1:0] num2;
integer fp;
integer i;
initial begin
for(i=8;i<12;i=i+1) begin
num2 = "0" +i -(i/10)*10;
if(i/10) num2[15:8] = "0" + i/10;
num32 = strfilter({`ULINE, num2, "_A_",int2str(i),".txt"},32);
$display("%s",num32);
fp = $fopen(num32);
$fwrite(fp,"%s",num32);
$fclose(fp);
end
end
endmodule
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